This disclosure relates to integrated circuits, and more particularly to a method and apparatus for selectively cooling a leakage control transistor in order to reduce overall standby leakage current therein.
With the scaling of semiconductor circuitry in integrated circuits, particularly in metal oxide semiconductor circuits, supply voltages are typically reduced to maintain circuit performance. This scaling, however, requires that the threshold voltages (VTH) be scaled as well, which increases the sub-threshold leakage current of metal oxide transistors in the semiconductors circuit. As scaling continues, this sub-threshold leakage current is becoming a more significant fraction of the total power consumption in integrated circuit technologies. Higher leakage currents and, hence, higher power leakage can be particularly problematic for mobile and hand-held applications that utilize battery power sources, for example.
An approach to reducing the amount of power lost due to sub-threshold leakage current has been the use of leakage control transistors (referred to also as xe2x80x9ckeeperxe2x80x9d devices) that disconnect logic blocks of a microprocessor from power or ground rails during standby modes when the digital logic block is disabled (not clocked). This approach utilizes transistor stack effect wherein a series connection of a logic block circuit and a leakage control transistor achieve reduction of leakage current on an order of a magnitude compared to either the logic block or the leakage control transistor on their own. In operation, if the logic block circuit is operated, the keeper device is turned on to power up the logic block. In turn, the standby current drawn by the keeper device determines the standby power dissipated by the logic block that is disabled by the keeper device. The keeper device is typically sized to compromise between a low standby current, thereby minimizing the amount of standby current, and a high saturation current in order to minimize the impact of the keeper device on performance of the digital logic block circuit.
Another approach to reducing leakage power and, hence, the overall power, is to reduce the temperature of the integrated circuit die. In particular, leakage current (IOFF) increases exponentially with temperature and, thus, leakage power can be represented as a function of temperature. By reducing transistor circuit junction temperatures, a significant reduction in the sub-threshold leakage currents may be achieved. Moreover, circuits operating at lower temperatures also benefit from higher mobility and, thus, higher saturation currents, which yields higher performance. A disadvantage of presently available cooling solutions, however, is that they are power inefficient. That is, the power required to decrease the circuit temperatures by active cooling is equivalent to or higher than the power savings gained by operating at lower temperature.